The fabrication of modem integrated circuits (ICs) involves the formation of features that make up devices, such as transistors and capacitors, and the interconnection of such devices to achieve a desired electrical function. Since the cost of fabricating ICs is inversely related to the number of ICs per wafer, there is a continued demand to produce a greater number of ICs per wafer. With the advent of new photolithographic techniques, fabrication of features with increasingly smaller dimensions was made possible, thereby increasing the density of devices which in turn increases the number of ICs per wafer.
In particular, the fabrication of random access memories (RAMs), such as dynamic random access memories (DRAMs), has fostered significant advances in improving device density. Typically, DRAMs comprise memory cells that are configured in rows (wordlines) and columns (bitlines) to provide storage of information. A memory cell comprises a pass transistor connected to, for example, a storage capacitor referred to as the "node" or "storage node". The pass transistor comprises a source, a drain, and a gate. Oppositely charged dopants having varying concentrations are, for example, ion implanted or diffused into the semiconductor substrate to form the source, channel which is located beneath the gate, and drain of the transistor. These various oppositely charged doped regions may be referred to in the art as retrograde or contradoped wells. Generally in a DRAM cell, the source corresponds to the bitline, the gate corresponds to the wordline, and the drain is coupled to the node. Support circuitry, such as row and column address decoders, drivers, and sense amplifiers, are used to activate the desired cell or cells within the array of cells. When a cell is activated, the transistor allows data to be read or written into the node.
An important consideration in designing the pass transistor is its off current (I.sub.off) characteristic. The I.sub.off is directly related to the leakage current of the storage node. Thus, I.sub.off impacts the retention time of the storage node. I.sub.off is determined by the dopant profile in the channel. This dopant profile controls the gate threshold voltage (V.sub.t). As the dimensions of the transistors become smaller, the dopant concentration of the V.sub.t implant needs to be increased to achieve reasonable I.sub.off characteristics, resulting in adequate storage node retention time.
However, increasing the dopant concentration of the channel to decrease I.sub.off produces high fields on the node side of the channel. Such high fields increases leakage current from the node, countering the effect of increased V.sub.t.
From the above discussion, it is apparent that there is a need to provide a device with reasonable I.sub.off and low leakage current.